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SAT-Based Scalable Formal Verification Solutions by Malay Ganai & A. Gupta HC
US $9.00
ApproximatelyS$ 11.58
Condition:
Like New
A book in excellent condition. Cover is shiny and undamaged, and the dust jacket is included for hard covers. No missing or damaged pages, no creases or tears, and no underlining/highlighting of text or writing in the margins. May be very minimal identifying marks on the inside cover. Very minimal wear and tear.
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Free local pickup from Woburn, Massachusetts, United States.
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Located in: Woburn, Massachusetts, United States
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eBay item number:395251052347
Item specifics
- Condition
- ISBN
- 9780387691664
About this product
Product Identifiers
Publisher
Springer
ISBN-10
0387691669
ISBN-13
9780387691664
eBay Product ID (ePID)
57237784
Product Key Features
Number of Pages
Xxx, 330 Pages
Language
English
Publication Name
Sat-Based Scalable Formal Verification Solutions
Subject
Cad-Cam, Electronics / Circuits / Integrated, Electronics / Circuits / General, Electrical
Publication Year
2007
Type
Textbook
Subject Area
Computers, Technology & Engineering
Series
Integrated Circuits and Systems Ser.
Format
Hardcover
Dimensions
Item Height
0.4 in
Item Weight
24.9 Oz
Item Length
9.3 in
Item Width
6.1 in
Additional Product Features
Intended Audience
Scholarly & Professional
LCCN
2007-922183
Dewey Edition
22
Number of Volumes
1 vol.
Illustrated
Yes
Dewey Decimal
621.3815/48
Table Of Content
Design Verification Challenges.- Design Verification Challenges.- Background.- Basic Infrastructure.- Efficient Boolean Representation.- Hybrid DPLL-Style SAT Solver.- Falsification.- SAT-Based Bounded Model Checking.- Distributed SAT-Based BMC.- Efficient Memory Modeling in BMC.- BMC for Multi-Clock Systems.- Proof Methods.- Proof by Induction.- Unbounded Model Checking.- Abstraction/Refinement.- Proof-Based Iterative Abstraction.- Verification Procedure.- SAT-Based Verification Framework.- Synthesis for Verification.
Synopsis
This book provides an engineering insight into how to provide a scalable and robust verification solution with ever increasing design complexity and sizes. It describes SAT-based model checking approaches and gives engineering details on what makes model checking practical. The book brings together the various SAT-based scalable emerging technologies and techniques covered can be synergistically combined into a scalable solution., Functional Verification has become an important aspect of the design process. Significant resources, both in industry and academia, are devoted to bridging the gap between design complexity and verification efforts. This book provides an engineering insight into how to provide a scalable and robust verification solution with ever increasing design complexity and sizes. With growing interests in SAT-based approaches for formal verification and increasing dissatisfaction twoard BDD-based approaches, this book brings together the various SAT-based scalable emerging technologies. Though the approaches described in the book are based on well-founded mathematics, the discussion is generally restricted to the engineering aspect for the ease of readability. Readers will also be exposed to the specific strengths of the various approaches in regard to the applicability., Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors' practical experiences and recommendations in verifying the large industry designs using VeriSol. The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products., Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors? practical experiences and recommendations in verifying the large industry designs using VeriSol. The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.
LC Classification Number
TA345-345.5
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